Formation of predictable and reliable capacitors in microelectronic devices may be desirable for several reasons. For example, mixed signal, radio frequency, and other circuits or devices may desirably include integrated capacitors with predictable and reliable electrical characteristics. Moreover, these devices often preferably include capacitors with low voltage coefficients (change of capacitance with voltage over an operating voltage range), good capacitor matching, and relatively predictable capacitor values. If capacitors form part of an integrated circuit, it may also be desirable to minimize additional processes or changes to processes required to form the capacitor. In other words, it is desirable to reduce the number of processes that are capacitor formation specific. Accordingly, it is often desirable to form such capacitors using substantially standard semiconductor process flows such as CMOS, bipolar, and BiCMOS processes.
Capacitors for microelectronic devices and the like may be formed in a variety of configurations. Often, such capacitors may be in the form of a thin-film capacitor and include two substantially parallel layers of conductive material separated by an insulating layer. Conductive materials typically include doped silicon substrate, polysilicon, or metal; insulating materials typically include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, barium strontium titanate, or other insulating materials.
The thin-film capacitor is generally formed by depositing, patterning, and etching various layers on a substrate. Typically, a first parallel layer of conductive material (a base plate) is formed by depositing the conductive material over the surface of the substrate, wherein the substrate may be a semiconductor wafer with several layers of conducting, insulating, semiconducting and semi-insulating layers thereon. Alternatively, the conductive material may be formed by doping the semiconductor substrate or another layer with substantially conductive material.
If the base plate is formed by depositing conductive material on the wafer surface, the material may be patterned with photoresist and etched using an appropriate wet or dry etch process. Similarly, and regardless of how the base plate was formed, the insulating layer may be formed by depositing insulating material over the surface of the wafer, patterning the insulating material, and etching the insulating material leaving at least some insulating material over at least a portion of the conducting layer. A second conducting plate (top plate of the capacitor) may be formed over the insulating layer in a like manner.
Typical capacitor materials and configurations of top and base capacitor plates known in the art generally include: a polysilicon top plate and a doped substrate base plate, a polysilicon top plate and a polysilicon base plate, a metal top plate and a polysilicon base plate, a metal top plate and a doped substrate plate, and a metal top plate and a metal base plate. Of these various capacitor configurations, the metal-to-metal capacitors, which have relatively low plate sheet resistance, may be particularly advantageous because, among other reasons, the capacitor generally has reduced parasitic capacitance because it allows for increased distance between the metal layers and the substrate (i.e., the base plate may be formed above the substrate surface). The metal-to-metal capacitors also generally have lower voltage coefficients due to reduced voltage induced depletion effects at the metal-to-insulator interface. In addition, because the metal plates of the capacitors have relatively low sheet resistance, the capacitors have relatively low series resistance, which allows capacitors with high a large Q factor to be constructed on the surface of a substrate. Capacitors with large Q factors may be particularly beneficial for use in RF circuits.
In an effort to reduce device and circuit costs, it is generally preferred to reduce the size of the devices and circuits and their corresponding capacitors. Capacitor size, for a given capacitance, may be reduced by increasing the capacitor's capacitance density. The increase in capacitance density can be achieved by using insulating layers with higher dielectric constant, by reducing the thickness of the insulating layer (i.e., the distance between the top and base plate of the capacitor), or a combination thereof.
The preferred distance between conducting layers for a given dielectric material is often governed by voltage breakdown design parameters, and the breakdown voltage parameters are generally dependent upon, among other things, the minimum distance between conducting layers. If either the insulating layer or the conducting layers, or a combination thereof have rough surfaces, the insulating layer thickness may have to be increased to compensate for the thinner regions of the layer such that the thinnest portion of the insulating layer provides adequate (e.g., sufficiently high) breakdown voltage characteristics.
One method of smoothing a surface of the insulating or conducting layer is to use chemical mechanical planarization (CMP), also known as chemical mechanical polishing. A capacitor formed by using CMP to form the top and bottom plates of a capacitor is disclosed in U.S. Pat. No. 5,708,559, issued to Brabazon et al. on Jan. 13, 1998. The '559 patent discloses methods of forming a capacitor on a surface of a wafer by forming a trench in an insulation layer, depositing metal over the insulation layer and planarizing the surface of the wafer to form the bottom plate of the capacitor. A thin layer dielectric is then deposited and patterned over the first capacitor plate, and this layer is patterned and etched such that a portion of the first metal plate of the capacitor is exposed. A second insulator is then deposited on the wafer surface and openings are etched into the second insulating material. A second metal layer is then deposited on top of the insulating layer, filling the openings, thereby forming a contact to the first and second plates of the capacitor.
While the '559 patent discloses methods for forming thin-film, metal-insulator-metal capacitors on a surface of a wafer, the disclosed processes generally include either excess or additional photoresist masking steps to form the capacitor plates, which may increase overall wafer fabrication costs, or the methods include etch stops on a part of the dielectric that communicates with the top capacitor plate. Use of such etch stops may cause variation of capacitance values due to capacitor formation processing and the like. In addition, the disclosed methods generally require etching through thick insulating layers to define the capacitor area. Etching of these thick layers typically results in increased variation of the trench dimensions that define the plate dimensions. This variation may in turn cause increased variation in the electrical properties of the capacitor such as capacitor matching. In addition, the processes disclosed in the '559 patent may include additional processing steps to form electrical contacts to the bottom metal plate capacitor. Simplified, cost-effective, and well defined capacitor flows are therefore desirable. In addition, capacitor formation processes that allow for capacitor formation at various levels or layers on a substrate may be desirable.
Capacitor characteristics, including capacitor reliability, may also depend on the integrity of the capacitor perimeter (e.g., the perimeter of the base plate, insulator, top plate, or a combination thereof). Prior-art capacitor formation processes typically expose the perimeter of the capacitor, particularly the perimeter of the dielectric material, to subsequent semiconductor processing steps such as interlayer dielectric deposition, etch, and the like. Such exposure may degrade the capacitor characteristics or render the characteristics unpredictable. Accordingly, methods of forming the capacitor that protect the capacitor perimeter during the formation are desirable.